lowRISC / opentitan
OpenTitan: Open source silicon root of trust
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OpenTitan: Open source silicon root of trust
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
SystemVerilog modules and classes commonly used for verification
RISC-V Debug Support for our PULP RISC-V Cores
APB Timer Unit
Generic Register Interface (contains various adapters)
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
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