The-OpenROAD-Project / OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
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OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
PicoRV32 - A Size-Optimized RISC-V CPU
Litex Reference Designs provides reference designs created out of IP Catalog using Litex integration capabilities.
Verilog AXI components for FPGA implementation
The USRP™ Hardware Driver Repository
Verilog Ethernet components for FPGA implementation
SERV - The SErial RISC-V CPU
HDL libraries and projects
RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
Plugins for Yosys developed as part of the F4PGA project.
FPGA implementation of the 6502.
RISC-V System on Chip Template